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Embedded Systems Software Engineer | Systems & Kernel Specialist
About Me
I am an embedded software engineer specializing in safety-critical, real-time systems. Most of my work involves hardware-software co-design, developing low-level device drivers, writing deterministic firmware for coprocessors, and optimizing memory pipelines under hard real-time scheduling constraints.
This page is a simple tribute to classic academic homepages. Here you will find no telemetry, tracking cookies, or bloated frameworks. Just clean text, basic C code, and simple terminal-style controls.
Professional Background
Over the past 8+ years, I have built software and drivers across several safety-critical domains:
-
Aerospace & Defense Systems:
- Linux & Barebox SoC Integration: Developed bootloader and OS bring-up strategies for a custom Cortex-A75 SoC, managing the secure boot chain from BootROM through Barebox initialization and handoff to the Linux kernel.
- ARM Architecture Optimization: Engineered assembly and C-level ARCH optimizations targeting ARMv8-A pipelines, using cache-aware layouts, lock-free queues, and ARM Assembly (AArch64) tuning to optimize data ingestion on high-throughput DMA engines.
- IRAD Rust Research: Led Independent Research and Development (IRAD) investigating Rust's memory-safety guarantees and compiler validation models for real-time safety-critical defense software.
- Training & Simulation Engineering: Developed C software for flight weapons simulators, maintaining low-latency, multi-threaded subsystems on VxWorks under hard real-time execution bounds.
- Industrial Automation Systems: Constructed C++ backend components for distributed industrial control loop engines, managing cascade and PID scheduling deadlines.
My toolchain of choice includes GCC/Clang, Yocto, GDB/JTAG debuggers, and Vim. I primarily write in C, C++, and ARM Assembly, and write secondary utilities in Rust.
Research & Development Laboratory
Notes on HDL/FPGA hardware design, QEMU system emulation, and device modeling.
1. HDL & FPGA Core Prototyping
Co-designing software and custom hardware accelerators requires modeling system buses and logical pipelines. I use SystemVerilog and VHDL to prototype soft cores, register interfaces, and custom DMA logic implemented on FPGA fabric. Offloading processing pipelines to dedicated hardware logic provides deterministic cycle bounds for timing-critical loops.
Below is a SystemVerilog example of a hardware status register interface designed to capture real-time signals for a primary CPU bus register read:
// reg_interface.sv - Custom Register Bus Interface
module reg_interface (
input logic clk,
input logic rst_n,
input logic sel,
input logic [3:0] addr,
input logic write,
input logic [31:0] wdata,
output logic [31:0] rdata,
input logic [31:0] hw_status
);
logic [31:0] ctrl_reg;
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
ctrl_reg <= 32'h0;
end else if (sel && write) begin
case (addr)
4'h0: ctrl_reg <= wdata;
default: ;
endcase
end
end
always_comb begin
rdata = 32'h0;
if (sel && !write) begin
case (addr)
4'h0: rdata = ctrl_reg;
4'h4: rdata = hw_status; // Read-only status registers
default: rdata = 32'hDEADBEEF;
endcase
end
end
endmodule2. QEMU Device Emulation & Virtual Prototyping
Developing bootloaders (such as Barebox) and low-level kernel drivers before custom silicon target designs are completed requires cycle-accurate modeling interfaces. I write custom QEMU machine configurations and peripheral model structures in C to support virtualization.
By modeling interrupt handlers (IRQs), DMA registers, and memory-mapped address tables in QEMU, the exact same driver code can be tested and verified inside automated virtual integration environments, mitigating hardware supply bottlenecks and validating early architecture layouts.
System Terminal
Interactive shell interface for CBERRY virtual environment.